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(R)
January 2004
CT RO D U T LETE P TE PRODUC OBSO TITU BS L E S U A3 0 9 6 HF POSSIB
CA3096, CA3096A, CA3096C
NPN/PNP Transistor Arrays
Description
The CA3096C, CA3096, and CA3096A are general purpose high voltage silicon transistor arrays. Each array consists of five independent transistors (two PNP and three NPN types) on a common substrate, which has a separate connection. Independent connections for each transistor permit maximum flexibility in circuit design. Types CA3096A, CA3096, and CA3096C are identical, except that the CA3096A specifications include parameter matching and greater stringency in ICBO , ICEO , and VCE(SAT). The CA3096C is a relaxed version of the CA3096.
Applications
* Five-Independent Transistors - Three NPN and - Two PNP * Differential Amplifiers * DC Amplifiers * Sense Amplifiers * Level Shifters * Timers * Lamp and Relay Drivers * Thyristor Firing Circuits * Temperature Compensated Amplifiers * Operational Amplifiers
CA3096, CA3096A, CA3096C Essential Differences
CHARACTERISTIC V(BR)CEO (V) (Min) CA3096A CA3096 CA3096C
Part Number Information
PART NUMBER (BRAND) CA3096AE CA3096AM (3096A) CA3096AM96 (3096A) CA3096CE CA3096E CA3096M (3096) CA3096M96 (3096) TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC Tape and Reel 16 Ld PDIP 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC Tape and Reel PKG. NO. E16.3 M16.15 M16.15 E16.3 E16.3 M16.15 M16.15
NPN PNP V(BR)CBO (V) (Min) NPN PNP hFE at 1mA NPN PNP hFE at 100A PNP ICBO (nA) (Max) NPN PNP
35 -40
35 -40
24 -24
45 -40
45 -40
30 -24
150-500 20-200
150-500 20-200
100-670 15-200
40-250
40-250
30-300
Pinout
CA3096, CA3096A, CA3096C (PDIP, SOIC) TOP VIEW
1 2 Q1 3 4 5 6 7 8 Q3 Q2 Q4 Q5 14 13 12 11 10 9 16 15 SUBSTRATE
40 -40
100 -100
100 -100
ICEO (nA) (Max) NPN PNP VCE SAT (V) (Max) NPN |VIO| (mV) (Max) NPN PNP |IIO| (A) (Max) NPN PNP 0.6 0.25 5 5 0.5 0.7 0.7 100 -100 1000 -1000 1000 -1000
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2004. All Rights Reserved 1 All other trademarks mentioned are the property of their respective owners.
FN595.5
CA3096, CA3096A, CA3096C
Absolute Maximum Ratings
NPN PNP Collector-to-Emitter Voltage, VCEO CA3096, CA3096A . . . . . . . . . . . . . . . . . . . . . 35V -40V CA3096C . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24V -24V Collector-to-Base Voltage, VCBO CA3096, CA3096A . . . . . . . . . . . . . . . . . . . . . 45V -40V CA3096C . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30V -24V Collector-to-Substrate Voltage, VCIO (Note 1) CA3096, CA3096A . . . . . . . . . . . . . . . . . . . . . 45V CA3096C . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30V Emitter-to-Substrate Voltage, VEIO CA3096, CA3096A . . . . . . . . . . . . . . . . . . . . . . -40V CA3096C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -24V Emitter-to-Base Voltage, VEBO CA3096, CA3096A . . . . . . . . . . . . . . . . . . . . . . 6V -40V CA3096C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V -24V -10mA Collector Current, IC (All Types). . . . . . . . . . . . 50mA Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Operating Conditions Thermal Information
Thermal Resistance (Typical, Note 2)
JA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Maximum Power Dissipation (Each Transistor, Note 3) . . . . . 200mW Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. The collector of each transistor of the CA3096 is isolated from the substrate by an integral diode. The substrate (Terminal 16) must be connected to the most negative point in the external circuit to maintain isolation between transistors and to provide for normal transistor action. 2. JA is measured with the component mounted on an evaluation PC board in free air. 3. Care must be taken to avoid exceeding the maximum junction temperature. Use the total power dissipation (all transistors) and thermal resistances to calculate the junction temperature.
Electrical Specifications
For Equipment Design, At TA = 25oC CA3096 MIN TYP MAX MIN CA3096A TYP MAX MIN CA3096C TYP MAX UNITS
PARAMETER
TEST CONDITIONS
DC CHARACTERISTICS FOR EACH NPN TRANSISTOR ICBO ICEO V(BR)CEO V(BR)CBO V(BR)CIO V(BR)EBO VZ VCE SAT VBE (Note 4) hFE (Note 4) |VBE/T| (Note 4) VCB = 10V, IE = 0 VCE = 10V, IB = 0 IC = 1mA, IB = 0 IC = 10A, IE = 0 ICI = 10A, IB = IE = 0 IE = 10A, IC = 0 IZ = 10A lC = 10mA, IB = 1mA IC = 1mA, VCE = 5V IC = 1mA, VCE = 5V 35 45 45 6 6 0.6 150 0.001 0.006 50 100 100 8 7.9 0.24 0.69 390 1.9 100 1000 9.8 0.7 0.78 500 35 45 45 6 6 0.6 150 0.001 0.006 50 100 100 8 7.9 0.24 0.69 390 1.9 40 100 9.8 0.5 0.78 500 24 30 30 6 6 0.6 100 0.001 0.006 35 80 80 8 7.9 0.24 0.69 390 1.9 100 1000 9.8 0.7 0.78 670 mV/oC nA nA V V V V V V V
DC CHARACTERISTICS FOR EACH PNP TRANSISTOR ICBO VCB = -10V, IE = 0 -0.06 -100 -0.006 -40 -0.06 -100 nA
2
CA3096, CA3096A, CA3096C
Electrical Specifications
For Equipment Design, At TA = 25oC (Continued) CA3096 MIN -40 -40 -40 40 -0.5 40 20 TYP -0.12 -75 -80 -100 100 -0.16 -0.6 85 47 2.2 MAX -1000 -0.4 -0.7 250 200 MIN -40 -40 -40 40 -0.5 40 20 VZ VCE SAT VBE hFE CA3096A TYP -0.12 -75 -80 -100 100 -0.16 -0.6 85 47 2.2 MAX -100 -0.4 -0.7 250 200 MIN -24 -24 -24 24 -0.5 30 15 CA3096C TYP -0.12 -30 -60 -80 80 -0.16 -0.6 85 47 2.2 MAX -1000 -0.4 -0.7 300 200 mV/oC UNITS nA V V V V V V
PARAMETER ICEO V(BR)CEO V(BR)CBO V(BR)EBO V(BR)ElO VCE SAT VBE (Note 4) hFE (Note 4)
TEST CONDITIONS VCE = -10V, IB = 0 IC = -100A, IB = 0 IC = -10A, IE = 0 IE = -10A, IC = 0 IEI = 10A, IB = I C = 0 IC = -1mA, IB = -100A IC = -100A, VCE = -5V IC = -100A, VCE = -5V IC = -1mA, VCE = -5V
|VBE/T| (Note 4) ICBO ICEO
IC = -100A, VCE = -5V
Collector-Cutoff Current Collector-Cutoff Current
Emitter-to-Base Zener Voltage Collector-to-Emitter Saturation Voltage Base-to-Emitter Voltage DC Forward-Current Transfer Ratio
V(BR)CEO Collector-to-Emitter Breakdown Voltage V(BR)CBO Collector-to-Base Breakdown Voltage V(BR)CIO Collector-to-Substrate Breakdown Voltage
V(BR)EBO Emitter-to-Base Breakdown Voltage NOTE: 4. Actual forcing current is via the emitter for this test.
|VBE/T| Magnitude of Temperature Coefficient: (for each transistor)
Electrical Specifications
For Equipment Design At TA = 25oC (CA3096A Only) CA3096A
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
FOR TRANSISTORS Q1 AND Q2 (AS A DIFFERENTIAL AMPLIFIER) Absolute Input Offset Voltage Absolute Input Offset Current Absolute Input Offset Voltage Temperature Coefficient |VIO| |IIO| V IO ----------------T VCE = 5V, IC = 1mA 0.3 0.07 1.1 5 0.6 mV A V/oC
FOR TRANSISTORS Q4 AND Q5 (AS A DIFFERENTIAL AMPLIFIER) Absolute Input Offset Voltage Absolute Input Offset Current Absolute Input Offset Voltage Temperature Coefficient |VIO| |IIO| V IO ----------------T VCE = -5V, IC = -100A RS = 0 0.15 2 0.54 5 250 mV nA V/oC
3
CA3096, CA3096A, CA3096C
Electrical Specifications
PARAMETER Typical Values Intended Only for Design Guidance At TA = 25oC TYPICAL VALUES
SYMBOL
TEST CONDITIONS
UNITS
DYNAMIC CHARACTERISTICS FOR EACH NPN TRANSISTOR Noise Figure (Low Frequency) Low-Frequency, Input Resistance Low-Frequency Output Resistance Admittance Characteristics Forward Transfer Admittance yFE Input Admittance yIE Output Admittance yOE Gain-Bandwidth Product fT gFE bFE gIE bIE gOE bOE f = 1MHz, VCE = 5V, IC = 1mA f = 1MHz, VCE = 5V, IC = 1mA f = 1MHz, VCE = 5V, IC = 1mA f = 1MHz, VCE = 5V, IC = 1mA f = 1MHz, VCE = 5V, IC = 1mA f = 1MHz, VCE = 5V, IC = 1mA VCE = 5V, IC = 1.0mA VCE = 5V, IC = 5mA Emitter-To-Base Capacitance Collector-To-Base Capacitance Collector-To-Substrate Capacitance CEB CCB CCI VEB = 3V VCB = 3V VCI = 3V 7.5 -j13 2.2 j3.1 0.76 j2.4 280 335 0.75 0.46 3.2 mS mS mS mS mS mS MHz MHz pF pF pF NF RI RO f = 1kHz, VCE = 5V, IC = 1mA, RS = 1k f = 1.0kHz, VCE = 5V IC = 1 mA f = 1.0kHz, VCE = 5V IC = 1 mA 2.2 10 80 dB k k
DYNAMIC CHARACTERISTICS FOR EACH PNP TRANSISTOR Noise Figure (Low Frequency) Low-Frequency Input Resistance Low-Frequency Output Resistance Gain-Bandwidth Product Emitter-To-Base Capacitance Collector-To-Base Capacitance Base-To-Substrate Capacitance NF RI RO fT CEB CCB CBI f = 1kHz, IC = 100A, RS = 1k f = 1kHz, VCE = 5V, IC = 100A f = 1kHz, VCE = 5V, IC = 100A VCE = 5V, IC = 100A VEB = -3V VCB = -3V VBI = 3V 3 27 680 6.8 0.85 2.25 3.05 dB k k MHz pF pF pF
Typical Applications
(SUBSTRATE) 2 f1 500 0.1F 3 1k V+ = 10V 13 1k 0.1F f2 500 5 4 NOTE: F1 OR F2 < 10kHz 6 Q2 7 44003 8 0 -20 -10 f2 - f1 > 0 0 f1 = f 2 10 f1 - f2 > 0 20 9 OUTPUT 1 15 14 Q5 11 3k 10 Q4 OUTPUT VOLTAGE (V) 1 3k 12 1F 16 9 CENTER FREQUENCY: 1kHz 8 7 6 5 4 3 2
FREQUENCY DEVIATION (kHz)
FIGURE 1. FREQUENCY COMPARATOR USING CA3096
FIGURE 2. FREQUENCY COMPARATOR CHARACTERISTICS
4
CA3096, CA3096A, CA3096C Typical Applications
(Continued)
3 NTC SENSOR 2 + 120VAC 1 RP 6.8k 2W 7 Q3 8 9 16 5.1k Q1 100F 12V 11 10 10k 13 14 6 5 10k Q2 4 10k 5.1k 1k
G MT1 T2300B MT2
Q4 Q5 12 15
LOAD
FIGURE 3. LINE-OPERATED LEVEL SWITCH USING CA3096A OR CA3096
+6V
13 Q5 14
40841 MOSFET 20k 5k 5k
OUTPUT 15 11 10 Q4 12 1k 1 Q1 Q2 2 50M 5F 4 5 3 6 20k 8 7 3.9k 10k 9 Q3
1k
TIME DELAY CHANGES 7% FOR SUPPLY VOLTAGE CHANGE OF 10%
16
FIGURE 4. ONE-MINUTE TIMER USING CA3096A AND A MOSFET
5
CA3096, CA3096A, CA3096C Typical Applications
(Continued)
V+ 36 -------------T=I R OL IF IO = 1mA AND RL = 1k VT = 36mV V 1k 12 10 Q4 11 15 14 3 VIN 100 1k 8 Q3 7 V1 Q1 2 9 IO 1k 4 Q5 13 6 Q2 100 5 EO 0 t 2k RL 1k EO +VT VIN -VT t
FIGURE 5. CA3096A SMALL-SIGNAL ZERO VOLTAGE DETECTOR HAVING NOISE IMMUNITY
1.5V 13 Q5 14 15 11 Q4 12 1.5M 1 3 6 7 Q1 Q2 2 500k 5F 1k 4 2k 5 8 Q3 10 10k 2k 9 LAMP GE 2158D OR EQUIVALENT
16 (SUBSTRATE)
FIGURE 6. TEN-SECOND TIMER OPERATED FROM 1.5V SUPPLY USING CA3096
6
CA3096, CA3096A, CA3096C Typical Applications
(Continued)
+6V
100k 1% 10 INPUT 100k 1% 11 13 14 100k 1%
6.2k 1% 6 5 3
6.2k 1% OUTPUT
NOTES:
Q4 Q5 12 15 Q2 Q1 4 9 Q3 51k 1% 51k 1% 300 1% 7 1k 1% 16 -6V 8 5k 1% 2 1
5. Can be operated with either dual supply or single supply. 6. Wide-input common mode range +5V to -5V. 7. Low bias current: <1A.
FIGURE 7. CASCADE OF DIFFERENTIAL AMPLIFIERS USING CA3096A
70
60 VOLTAGE GAIN (dB)
50
40
30
20
10 1 10 100 FREQUENCY (kHz) 1000
FIGURE 8. FREQUENCY RESPONSE
7
CA3096, CA3096A, CA3096C Typical Performance Curves
10 COLLECTOR CUT-OFF CURRENT (pA) 104
103
ZENER CURRENT (mA)
1 VZ
102
VCE = 10V
10-1
10
VCE = 5V
1
10-2 7
7.5
8 ZENER VOLTAGE (V)
8.5
9
10-1 -100
-75
-50
-25
0
25
50
75
100
TEMPERATURE (oC)
FIGURE 9. BASE-TO-EMITTER ZENER CHARACTERISTIC (NPN)
FIGURE 10. COLLECTOR CUT-OFF CURRENT (ICEO) vs TEMPERATURE (NPN)
DC FORWARD CURRENT TRANSFER RATIO
103 COLLECTOR CUT-OFF CURRENT (pA)
500 TA = 85oC 400 TA = 25oC 300 TA = -40oC
102 VCB = 15V 10 VCB = 10V VCB = 5V 1
200
10-1
100
10-2 -75
-50
-25
0
25
50
75
100
0 0.01
TEMPERATURE (oC)
0.1 1 COLLECTOR CURRENT (mA)
10
FIGURE 11. COLLECTOR CUT-OFF CURRENT (ICBO) vs TEMPERATURE (NPN)
FIGURE 12. TRANSISTOR (NPN) hFE vs COLLECTOR CURRENT
0.9 VCE = 5V BASE TO EMITTER VOLTAGE (V) BASE TO EMITTER VOLTAGE (V) 0.8 0.9 IC = 10mA, 1.67mV/oC IC = 5mA, 1.77mV/oC IC = 1mA, 1.90mV/oC IC = 100A, 2.05mV/oC
0.8
0.7
0.7
0.6
0.6
0.5
0.5
0.4 0.01
0.1 1 COLLECTOR CURRENT (mA)
10
0.4 -40
-20
0
20
40
60
80
100
TEMPERATURE (oC)
FIGURE 13. VBE (NPN) vs COLLECTOR CURRENT
FIGURE 14. VBE (NPN) vs TEMPERATURE
8
CA3096, CA3096A, CA3096C Typical Performance Curves
(Continued)
1.0 COLLECTOR TO EMITTER SATURATION VOLTAGE (V) TA = 25oC = 10 TA = -40oC
COLLECTOR CUT-OFF CURRENT (pA)
TA = 85oC
104
103 VCE = -10V 102
VCE = -15V
0.8
0.6
VCE = -5V
0.4
10
0.2
0.1 0.1
1 1.0 10 COLLECTOR CURRENT (mA) 100 -50 -25 0 25 50 75 100 TEMPERATURE (oC)
FIGURE 15. VCE SAT (NPN) vs COLLECTOR CURRENT
FIGURE 16. COLLECTOR CUT-OFF CURRENT (ICEO) vs TEMPERATURE (PNP)
110 100 90 80 70 60 50 40 30 20 10 0 0.01 0.1 1.0 COLLECTOR CURRENT (mA) 10 VCE = 1V VCE = 5V VCE = 20V
VCB = -15V VCB = -10V 102 VCB = -5V
10
1 -50
-25
0
25
50
75
100
TEMPERATURE (oC)
FIGURE 17. COLLECTOR CUT-OFF CURRENT (ICBO) vs TEMPERATURE (PNP)
DC FORWARD CURRENT TRANSFER RATIO 100 VCE = 5V 80 IC = 10A 60 IC = 1mA 40
FIGURE 18. TRANSISTOR (PNP) hFE vs COLLECTOR CURRENT
DC FORWARD CURRENT TRANSFER RATIO
103 COLLECTOR CUT-OFF CURRENT (pA)
1.0 BASE TO EMITTER VOLTAGE (V) 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 VCE = 5V
IC = 100A
20
IC = 5mA
0 -40
-20
0
20
40
60
80
0 0.01
TEMPERATURE (oC)
0.1 1.0 COLLECTOR CURRENT (mA)
10
FIGURE 19. TRANSISTOR (PNP) hFE vs TEMPERATURE
FIGURE 20. VBE (PNP) vs COLLECTOR CURRENT
9
CA3096, CA3096A, CA3096C Typical Performance Curves
(Continued)
MAGNITUDE OF INPUT OFFSET VOLTAGE (mV) 80 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0.01 0.1 1.0 COLLECTOR CURRENT (mA) 10
0.9 BASE TO EMITTER VOLTAGE (V) IC = 5mA, VBE/T - 0.97mV/oC 0.8 IC = 1mA, -1.84mV/oC
0.7
0.6 IC = 100A, -2.2mV/oC 0.5
0.4 -40
-20
0
20 40 TEMPERATURE (oC)
60
FIGURE 21. VBE (PNP) vs TEMPERATURE
FIGURE 22. MAGNITUDE OF INPUT OFFSET VOLTAGE |VIO| vs COLLECTOR CURRENT FOR NPN TRANSISTOR Q1 - Q2
18 RSOURCE = 500 16
MAGNITUDE OF INPUT OFFSET VOLTAGE (mV)
0.5
0.4 NOISE FIGURE (dB)
14 12 10 1mA 8 6 100A 4 2 10A IC = 3mA
0.3
0.2
0.1
0 0.01
0.1 1 COLLECTOR CURRENT (mA)
10
0 0.01
0.1
1.0 FREQUENCY (kHz)
10
100
FIGURE 23. MAGNITUDE OF INPUT OFFSET VOLTAGE |VIO| vs COLLECTOR CURRENT FOR PNP TRANSISTOR Q4 - Q5
18 RSOURCE = 1k 16 14 NOISE FIGURE (dB) 12 10 8 6 4 2 0 0.01 100A 10A 1mA IC = 3mA
FIGURE 24. NOISE FIGURE vs FREQUENCY FOR NPN TRANSISTORS
28 RSOURCE = 10k 24 NOISE FIGURE (dB) 20 16 12 8 4 0 0.01 10A 100A IC = 3mA 1mA
0.1
1 FREQUENCY (kHz)
10
100
0.1
1.0 FREQUENCY (kHz)
10
100
FIGURE 25. NOISE FIGURE vs FREQUENCY FOR NPN TRANSISTORS
FIGURE 26. NOISE FIGURE vs FREQUENCY FOR NPN TRANSISTORS
10
CA3096, CA3096A, CA3096C Typical Performance Curves
28 24 NOISE FIGURE (dB) 20 IC = 1mA 16 100A 12 10A 8 4 10A 0 0.01 0 0.1 1 FREQUENCY (kHz) 10 100 0.1 1.0 COLLECTOR CURRENT (mA) 10 100A
(Continued)
400 GAIN-BANDWIDTH PRODUCT (MHz) VCE = 5V
RSOURCE = 100k RSOURCE = 1M
300
200
100
FIGURE 27. NOISE FIGURE vs FREQUENCY FOR NPN TRANSISTORS
FIGURE 28. GAIN-BANDWIDTH PRODUCT vs COLLECTOR CURRENT (NPN)
4.0 3.5 CAPACITANCE (pF) 3.0 CCI 2.5 2.0 1.5 1.0 0.5 CEB CCB INPUT RESISTANCE (k)
1000 f = 1kHz
100
NPN PNP
10
0
1
2
3
4
5
6
7
8
9
10
1 0.01
0.1
1
10
BIAS VOLTAGE (V)
COLLECTOR CURRENT (mA)
FIGURE 29. CAPACITANCE vs BIAS VOLTAGE (NPN)
FIGURE 30. INPUT RESISTANCE vs COLLECTOR CURRENT
104
FORWARD TRANSFER CONDUCTANCE (gFE) OR FORWARD TRANSFER SUSCEPTANCE (bFE) (mS)
f = 1kHz
40 gFE IC = 1mA
OUTPUT RESISTANCE (k)
30
103 PNP 102
NPN
20
10 gFE 100A 0 bFE 100A -10 bFE 1mA
10
1 0.01
0.1
1.0
10
-20 1 10 FREQUENCY (MHz) 100
COLLECTOR CURRENT (mA)
FIGURE 31. OUTPUT RESISTANCE vs COLLECTOR CURRENT
FIGURE 32. FORWARD TRANSCONDUCTANCE vs FREQUENCY
11
CA3096, CA3096A, CA3096C Typical Performance Curves
6 INPUT CONDUCTANCE (gIE) OR INPUT SUSCEPTANCE (bIE) (mS) gIE bIE IC = 10mA 2.5
(Continued)
OUTPUT CONDUCTANCE (gOE) OR OUTPUT SUSCEPTANCE (bOE) (mS)
5
IC = 1mA bOE
4
10mA 100A 10A 1mA 1mA
2.0 100A bOE
3
1.5
2
1.0 100A gOE
1mA gOE
1
100A 10A 1 10 FREQUENCY (MHz) 100
0.5
0
0
1
10 FREQUENCY (MHz)
100
FIGURE 33. INPUT ADMITTANCE vs FREQUENCY
30 RSOURCE = 500
FIGURE 34. OUTPUT ADMITTANCE vs FREQUENCY
30 RSOURCE = 1k
NOISE FIGURE (dB)
20 IC = 1mA 10A 10 100A
NOISE FIGURE (dB)
20
10A 10 100A
IC = 1mA
0 0.01
0.1
1.0 FREQUENCY (kHz)
10
100
0 0.01
0.1
1 FREQUENCY (kHz)
10
100
FIGURE 35. NOISE FIGURE vs FREQUENCY (PNP)
40 RSOURCE = 10k GAIN-BANDWIDTH PRODUCT (MHz) 8
FIGURE 36. NOISE FIGURE vs FREQUENCY (PNP)
VCE = 5V
30 NOISE FIGURE (dB)
7
IC = 1mA 20
6
10 10A 0 0.01 0.1
100A
5
1.0 FREQUENCY (kHz)
10
100
4 0.1
1.0 COLLECTOR CURRENT (mA)
10
FIGURE 37. NOISE FIGURE vs FREQUENCY (PNP)
FIGURE 38. GAIN-BANDWIDTH PRODUCT vs COLLECTOR CURRENT (PNP)
12
CA3096, CA3096A, CA3096C Typical Performance Curves
6
(Continued)
5 CAPACITANCE (pF)
4
3 CBC 2 CBE
CBI
1 0 0 1 2 3
4
5
6
7
8
9
10
BIAS VOLTAGE (V)
FIGURE 39. CAPACITANCE vs BIAS VOLTAGE (PNP)
Metallization Mask Layout
CA3096H
0 40 10 20 30 40
30
Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch).
37-45 (0.940-1.143)
20
10
The photographs and dimensions represent a chip when it is part of the wafer. When the wafer is cut into chips, the cleavage angles are 57 degrees instead of 90 degrees with respect to the face of the chip. Therefore, the isolated chip is actually 7mils (0.17mm) larger in both dimensions.
0
4-10 (0.102-0.254) 37-45 (0.940-1.143)
13
CA3096, CA3096A, CA3096C Dual-In-Line Plastic Packages (PDIP)
D BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1 A2 L A C L E
E16.3 (JEDEC MS-001-BB ISSUE D)
16 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 B MIN 0.015 0.115 0.014 0.045 0.008 0.735 0.005 0.300 0.240 MAX 0.210 0.195 0.022 0.070 0.014 0.775 0.325 0.280 MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 18.66 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 19.68 8.25 7.11 NOTES 4 4 8, 10 5 5 6 5 6 7 4 9 Rev. 0 12/93
-C-
eA eC
C
e
C A BS
eB
NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
B1 C D D1 E E1 e eA eB L N
0.100 BSC 0.300 BSC 0.115 16 0.430 0.150
2.54 BSC 7.62 BSC 2.93 16 10.92 3.81
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CA3096, CA3096A, CA3096C Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 H 0.25(0.010) M BM
M16.15 (JEDEC MS-012-AC ISSUE C)
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A
L SEATING PLANE -AD -CA h x 45o
MILLIMETERS MIN 1.35 0.10 0.33 0.19 9.80 3.80 MAX 1.75 0.25 0.51 0.25 10.00 4.00 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93
MIN 0.0532 0.0040 0.013 0.0075 0.3859 0.1497
MAX 0.0688 0.0098 0.020 0.0098 0.3937 0.1574
A1 B C D E

A1 0.10(0.004) C
e
B 0.25(0.010) M C AM BS
e H h L N
0.050 BSC 0.2284 0.0099 0.016 16 0o 8o 0.2440 0.0196 0.050
1.27 BSC 5.80 0.25 0.40 16 0o 6.20 0.50 1.27
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
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